Minimization of Average Power Consumption in 3 Stage CMOS Ring Oscillator based on MSFLA, Fuzzy-MSFLA, GA, and Fuzzy-GA

This article is based on the application of heuristic algorithms to minimize the average power consumption in a VLSI circuit. The idea is to find the optimum layout and temperature for a 3 stage ring oscillator with minimal dynamic average power. The objective function is the same as average power (Pavg) of 3 stage ring oscillator with 6 CMOS inverters that depends on the temperature and the two different group of channel widths for NMOSs and PMOSs. (W1=W3=W5 and W2=W4=W6). These parameters make a three dimensional search space which is explored by search agents of algorithms. Motivated by the convergence of Modified Shuffled Frog Leaping Algorithm (MSFLA), Genetic Algorithm (GA) and the link of MATLAB with HSPICE Software the minimized average power of 3 stage ring oscillator is obtained. Based on MSFLA, Fuzzy-MSFLA, GA, and Fuzzy-GA algorithms the best resulting for Pavg in 0. 18μm Technology and the supply voltage of 5v is 1. 19 μW based on Fuzzy-MSFLA.